Method and apparatus for robust automatic frequency control in cdma systems with constant pilot signals

ABSTRACT

There is provided a method for generating an error signal for an automatic frequency control (AFC) loop in a Code Division Multiple Access (CDMA) system. Sign information relating to phase differences in received pilot signals is accumulated. In one embodiment, the accumulated sign information is compared against predetermined threshold levels. The error signal is generated when at least one of the predetermined threshold levels is satisfied. In a second embodiment, the accumulated sign information is decimated. An output of the decimating step is utilized as the error signal for the AFC loop.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to wireless Code Division.Multiple Access (CDMA) systems and, more particularly, to automaticfrequency control (AFC) in CDMA systems with constant pilot signals.

2. Background of the Invention

In passband CDMA systems, the receivers usually need to generate a localcarrier to demodulate the received signal. An automatic frequencycontrol (AFC) operation of the CDMA systems generates a local carrierusing a frequency close to the transmitter carrier frequency, and alsotracks the deviation of the local frequency from the transmitterfrequency distorted by channel propagation. For CDMA systems, such as,for example, Interim Standard-96 (IS-95) and Universal MobileTelecommunications System (UMTS), a constant pilot signal is used toperform the AFC operation.

In CDMA systems, the pilot signal used for the AFC operation isdemodulated to the in-phase and quadrature baseband signal using thegenerated local carrier. However, the frequency of the local carrier isusually different from the frequency of the transmitter carrier. In UMTSsystems, due to component inaccuracies and channel variations, thefrequency difference could be as high as 10 KHz, which can have theeffect of severely degrading the receiver performance. An AFC loop istherefore exploited to reduce the frequency difference to a level thatintroduces only a negligible performance loss.

In AFC operation, a feedback loop is formed, commonly referred to as anAFC loop. In this loop, an error signal representing the differencebetween the local carrier and the transmitter carrier frequency iscomputed and filtered. The filtered output is then used to adjust thelocal carrier frequency. As such, the quality of the error signaldirectly affects the performance of the AFC loop.

In a conventional AFC loop in CDMA systems, pilot signals are firstdespread to obtain despread symbols. The phase difference between thecurrent despread symbol and the previous despread symbol is computed,representing the residual frequency offset between the local carrier andthe transmitter carrier. The phase difference signal is filtered using afirst-order or second-order loop filter in order to generate the errorsignal. However, due to the severe fading effect in wireless channels,this type of error signal usually has a large variation, even after thefiltering operation, and thus can make the AFC loop unstable. Manyproposed AFC loops are not robust in the presence of mobile channeldegradations.

Accordingly, it would be desirable and highly advantageous to have anAFC loop for a CDMA system that overcomes the above-described problemsof the prior art.

SUMMARY OF THE INVENTION

The problems stated above, as well as other related problems of theprior art, are solved by the present invention, which is directed to arobust Automatic Frequency Control (AFC) control for Code DivisionMultiple Access (CDMA) Systems with constant pilot signals,

According to an aspect of the present invention, there is provided amethod for generating an error signal for an automatic frequency control(AFC) loop in a CDMA system. Sign information relating to phasedifferences in received pilot signals is accumulated. The accumulatedsign information is compared against predetermined threshold levels. Theerror signal is generated when at least one of the predeterminedthreshold levels is satisfied.

According to another aspect of the present invention, there is provideda method for generating an error signal for an automatic frequencycontrol (AFC) loop in a CDMA system. Sign information relating to phasedifferences in received pilot signals is accumulated. The accumulatedsign information is decimated. An output of the decimating step isutilized as the error signal for the AFC loop.

These and other aspects, features and advantages of the presentinvention will become apparent from the following detailed descriptionof preferred embodiments, which is to be read in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an exemplary Automatic FrequencyControl (AFC) loop 100 for a Code Division Multiple Access (CDMA)system, according to an illustrative embodiment of the presentinvention; and

FIG. 2 is a flow diagram illustrating a method 200 for generating anerror signal for an Automatic Frequency Control (AFC) loop in a CodeDivision Multiple Access (CDMA) system, according to an illustrativeembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to methods and apparatus for robustAutomatic Frequency Control (AFC) in Code Division Multiple Access(CDMA) systems with constant pilot signals.

It is to be understood that the present invention may be implemented invarious forms of hardware, software, firmware, special purposeprocessors, or a combination thereof. Preferably, the present inventionis implemented as a combination of hardware and software. Moreover, thesoftware is preferably implemented as an application program tangiblyembodied on a program storage device. The application program may beuploaded to, and executed by, a machine comprising any suitablearchitecture. Preferably, the machine is implemented on a computerplatform having hardware such as one or more central processing units(CPU), a random access memory (RAM), and input/output (I/O)interface(s). The computer platform also includes an operating systemand microinstruction code. The various processes and functions describedherein may either be part of the microinstruction code or part of theapplication program (or a combination thereof) that is executed via theoperating system. In addition, various other peripheral devices may beconnected to the computer platform such as an additional data storagedevice and a printing device.

It is to be further understood that, because some of the constituentsystem components and method steps depicted in the accompanying Figuresare preferably implemented in software, the actual connections betweenthe system components (or the process steps) may differ depending uponthe manner in which the present invention is programmed. Given theteachings herein, one of ordinary skill in the related art will be ableto contemplate these and similar implementations or configurations ofthe present invention.

FIG. 1 is a diagram illustrating an exemplary Automatic FrequencyControl (AFC) loop 100 for a Code Division Multiple Access (CDMA)system, according to an illustrative embodiment of the presentinvention. The AFC loop 100 includes a Radio Frequency/IntermediateFrequency (RF/IF) analog chain 102, an Analog-to-Digital Converter (ADC)104, a rake receiver 106, a phase difference computing module 108, anaccumulator and decimator 110, a Low Pass Filter (LPF) 112, a gainmodule 114, a derotator 116, an averaging frequency offset controlmodule 118, a local oscillator 120, and a finger N control module 122.As used herein, the finger N control module 122 represents a respectivecopy of each of modules 108, 110, 112, 114, and 116 for each of thefingers of the rake receiver 106. That is, modules 108 through 116correspond to the first finger of the rake receiver 106 and copies ofthese modules are respectively repeated for each other finger of therake receiver 106 up to a N^(th) finger. It is to be appreciated thatthe rake receiver 106 has fingers 1 through N associated therewith, eachfinger serving as a receiving element.

An analog pilot signal is output from the RF/IF analog chain 102,converted to a digital signal by the ADC 104, and fed into the rakereceiver 106 where it is despread. The phase differences between thedespread pilot signal samples output from the rake receiver 106 arecomputed by the phase difference computing module 108. The signs [+1,−1] of the phase differences are accumulated in the accumulator anddecimator 110. The output of the accumulator and decimator 110 is anerror signal that is input to the LPF 112. The output signal of the LPF112 is applied to the gain module 114, which amplifies the signal asneeded. The output signal from the gain module 114 is input into thederotator 116 that completes a feedback loop with the fingers 1−(N−1) ofrake receiver 106. The derotator 116 performs the complex multiplicationthat is supposed to eliminate the frequency offset in the receiver.

Frequency offset control signals from the individual fingers of the rakereceiver are averaged by the averaging frequency offset control module118 and the resulting error signal that is output from module 118 isthen input to the local oscillator 120 to control the local oscillator120.

FIG. 2 is a flow diagram illustrating a method 200 for generating anerror signal for an Automatic Frequency Control (AFC) loop in a CodeDivision Multiple Access (CDMA) system, according to an illustrativeembodiment of the present invention.

The pilot signal is demodulated (202) with respect to the local carrier(220), and is then sampled and despread to obtain despread pilot symbolss[n] (step 204). For convenience, the despread pilot symbols s[n] aremodeled as follows:s[n]=A[n]exp(j2πΔfnT+φ[n])+w[n]where A[n]exp(φ[n]) represents the fading channel coefficient, Δfrepresents the frequency difference between the local carrier andtransmitter carrier, T represents the period of the despreadingoperation, and w[n] represents the noise plus the interference.

The despread pilot symbols s[n] are delayed by T(i.e., the period of thedispreading operation performed by the rake receiver 106) and conjugatedto produce s*[n−1] (step 206), which provides the reference pilot signalused for purposes such as data demodulation and synchronization. Amultiplication operation is then performed (208) as follows:s[n]s*[n−1]=A[n]A[n−1]exp(j2πΔfT+φ[n]−[n−1])+v[n],where v[n] accounts for the effect of the noise and interference. Thatis, the current despread pilot signal is multiplied with the complexconjugate of the previous despread pilot signal. Under slow fading and amoderately fast fading environment, it can be presumed that φ[n]≅φ[n−1]or the effect of noise and interference can be placed into the term v[n]to produce:s[n]s*[n−1]=A[n]A[n−1]exp(j2πΔfT)+v[n].Note that the angle of s[n]s*[n−1] can be an error signal indicating thefrequency difference between the local carrier and transmitter carrier.To compute the phase angle of s[n]s*[n−1] exactly, a division operationis required, which is undesirable in practical implementations. Thecommon approach is to use the imaginary part of s[n]s*[n−1], denoted asIm(s[n]s*[n−1]). However, Im(s[n]s*[n−1]) is noisy and its absolutevalue may have large variation due to the fading effects in the wirelesschannel.

Thus, instead of directly using the imaginary part of the productresulting from step 208 (i.e., Im(s[n]s*[n−1])) as in the prior art, thepresent invention advantageously extracts the sign value of theimaginary part (step 210) for use in computing the phase angle. The signvalue [+1 or −1] of the imaginary part of the product reflects thefrequency difference between the local carrier (generated by localoscillator 120) and the transmitter carrier. The sign value, which iseither equal to −1 or +1, is accumulated in the accumulator 110 (step212). That is, the sign value is added to the previous content in theaccumulator 110. The accumulator value output from the accumulator iscompared against two thresholds (+a and −b) (step 214). If one of thethresholds is satisfied, then an error signal is generated and theaccumulator value ACC is then reset to zero. (step 216). If theaccumulator value ACC is greater than the threshold +a, then a positiveconstant error signal +x is generated. If the accumulator value ACC isbelow the threshold −b, then a negative constant error signal −y isgenerated. The comparison step and the generation of the error signalare both performed by the accumulator and decimator 110. However, it isto be appreciated that in some embodiments of the present invention, aseparate comparator may be disposed in between the accumulator anddecimator 110 and the LPF 112 to perform the comparing and generatingsteps. In the case that the thresholds are not satisfied, then theaccumulator continues to accumulate values without resetting. It is tobe noted that values x and y act as gains in the control loop.

According to another embodiment of the present invention, theaccumulator and decimator 110, in addition to performing accumulation,also performs decimation. In this case, for every t (threshold) inputsamples, the decimator is reset to zero, and at the same interval theoutput of the decimator is passed as an error signal to the LPF 112. Inthis case, as opposed to the previously described one, there are nofixed gains x and y that need to be determined. Moreover, in this case,there are no thresholds +a and −b that need to be applied. As is known,a decimator having a certain input rate will correspondingly have areduced output rate, with each input symbol or bit being “stretched” orrepeated at the output to form a continuous output at the reduced rate.Thus, in this embodiment, the accumulator and decimator 110 performsboth accumulation and decimation, in contrast to other embodimentswherein the accumulator and decimator 306 is simply an accumulator thatperforms accumulation but not decimation.

The threshold values +a, −b and the constant error signals +x, −y can beadjusted to change the AFC loop characteristics. Such adjustments can bea function of the desired bandwidth and gain of the AFC loop. Changes tothe threshold values +a and −b will affect the bandwidth of the AFCloop, and changes to the constants +x and −y will affect the gain of theAFC loop. Changes to a, b, x and/or y can be done during the calibrationof the rake receiver 106, or adaptively as a function of the Dopplerestimation or other parameters that determine the optimal bandwidth ofthe AFC loop.

The generated error signal is further passed to the LPF 112 (step 218)to limit the noise in the signal, and the output of the LPF 112 is usedto adjust the frequency of the local carrier. By way of example, thecommonly used LPF is a second order low pass filter, as follows:i[n]=i[n−1]+β*e[n],out[n]=α*e[n]+i[n],where α and β are the filter coefficients, i[n] is the integral part ofthe LPF 112, α*e[n] is the proportional part of the LPF 112, and out[n]is the LPF 112 output. Those of ordinary skill in the art will recognizethat other loop filters may be implemented without departing from thespirit of the present invention.

Although the illustrative embodiments have been described herein withreference to the accompanying drawings, it is to be understood that thepresent invention is not limited to those precise embodiments, and thatvarious other changes and modifications may be affected therein by oneof ordinary skill in the related art without departing from the scope orspirit of the invention. All such changes and modifications are intendedto be included within the scope of the invention as defined by theappended claims.

1. A method for generating an error signal, comprising the steps of:accumulating sign information relating to phase differences in receivedsignals; comparing the accumulated sign information againstpredetermined threshold levels; and generating the error signal when atleast one of the predetermined threshold levels is satisfied.
 2. Themethod according to claim 1 wherein the error signal is generated in anautomatic frequency control (AFC) loop in a Code Division MultipleAccess (CDMA) system.
 3. The method according to claim 2, furthercomprising the steps of: multiplying a current despread pilot signalwith a complex conjugate of a previous despread pilot signal; andobtaining a sign value of a product of said multiplying step.
 4. Themethod according to claim 3, wherein said step of obtaining a sign valuecomprises the step of extracting the sign value of an imaginary part ofthe product of said multiplying step.
 5. The method according to claim1, wherein said predetermined threshold levels include a positivethreshold and a negative threshold.
 6. The method according to claim 5,wherein said generating step comprises the steps of generating apositive constant error signal when the positive threshold is satisfied,and generating a negative constant error signal when the negativethreshold level is satisfied.
 7. The method according to claim 6,wherein the positive constant error signal and the negative constanterror signal are used to control a gain of an AFC loop.
 8. The methodaccording to claim 1, further comprising the step of utilizing values ofthe error signal to control a gain in an AFC loop.
 9. The methodaccording to claim 8, wherein the values of the error signals areconstant values capable of being adjusted to control the gain in the AFCloop.
 10. The method according to claim 1, further comprising the stepof utilizing the predetermined threshold levels to affect a bandwidth ofan AFC loop.
 11. The method according to claim 1, further comprising thestep of resetting the accumulated sign information when the error signalis generated.
 12. A method for generating an error signal for anautomatic frequency control (AFC) loop in a Code Division MultipleAccess (CDMA) system, comprising the steps of: accumulating signinformation relating to phase differences in received pilot signals;decimating the accumulated sign information; and utilizing an output ofsaid decimating step as the error signal for the AFC loop.
 13. Themethod according to claim 12, further comprising the steps of:multiplying a current despread pilot signal with a complex conjugate ofa previous despread pilot signal; and obtaining a sign value of aproduct of said multiplying step.
 14. The method according to claim 13,wherein said step of obtaining the sign value comprises the step ofextracting the sign value of an imaginary part of the product of saidmultiplying step.
 15. The method according to claim 12, wherein theoutput of said decimating step is utilized as the loop error signal upona decimation of a threshold number of the samples.
 16. The methodaccording to claim 15, further comprising the step of resetting theoutput of said decimating step at a same interval as when the output ofsaid decimating step is utilized as the loop error signal.
 17. Anapparatus for generating an error signal, comprising: an accumulator foraccumulating sign information relating to phase differences in receivedpilot signals; a comparator for thresholding the accumulated signinformation against adaptable threshold levels; and an error signalgenerator for generating the error signal when at least one of theadaptable threshold levels is satisfied.
 18. The apparatus according toclaim 17, wherein said error signal generator generates a positiveconstant error signal when the positive threshold is satisfied, andgenerates a negative constant error signal when the negative thresholdlevel is satisfied.
 19. The apparatus according to claim 18, wherein thepositive constant error signal and the negative constant error signalare used to control a gain of an AFC loop.
 20. An apparatus forgenerating an error signal for an automatic frequency control (AFC) loopin a Code Division Multiple Access (CDMA) system, comprising: anaccumulator for accumulating sign information relating to phasedifferences in received pilot signals; a decimator for decimating theaccumulated sign information so as to output the error signal therefrom.21. The apparatus according to claim 20, wherein the output of saiddecimator is utilized as the error signal upon a decimation of athreshold number of the samples.
 22. The apparatus according to claim21, wherein the output of said decimator is reset at a same interval aswhen the output of said decimator is utilized as the error signal.
 23. Amethod for generating a loop error signal for a delay-lock code trackingloop in a CDMA system, comprising the steps of: accumulating signinformation relating to phase differences between samples of a receivedcode sequence; comparing the accumulated sign information againstadaptable threshold levels; and generating the loop error signal when atleast one of the adaptable threshold levels is satisfied.
 24. The methodaccording to claim 23, further comprising the steps of: calculating afirst integral corresponding to products of some of the samples and ascrambling code sequence; calculating a second integral corresponding toproducts of later occurring ones of the samples and the scrambling code;and subtracting the second integral from the first integral to obtainthe sign information.
 25. The method according to claim 24, wherein eachof the first integral and the second integral are calculated over a codetracking dwell time.
 26. The method according to claim 23, wherein saidaccumulating step accumulates the sign information from a sample errorsignal e[m], wherein e[m] is equal to${\sum\limits_{n = 0}^{N_{D} - 1}{{R_{E}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}{{Sc}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}}} - {\sum\limits_{n = 0}^{N_{D} - 1}{{R_{L}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}{{Sc}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}}}$wherein R_(E) and R_(L) respectively represent earlier occurring samplesand later occurring samples with respect to on-time occurring samples, nis an index of the samples in a chip rate, N_(D) is a code trackingdwell time, Sc is a local scrambling code sequence, and m is an index ofthe sample error signal e[m].
 27. The method according to claim 23,wherein the adaptable threshold levels include a positive threshold anda negative threshold.
 28. The method according to claim 27, wherein saidgenerating step comprises the step of generating a positive constantloop error signal when the positive threshold is satisfied, andgenerating a negative constant loop error signal when the negativethreshold level is satisfied.
 29. The method according to claim 28,wherein the positive constant loop error signal and the negativeconstant loop error signal are used to control a gain of the delay-lockcode tracking loop.
 30. The method according to claim 23, furthercomprising the step of utilizing values of the loop error signal tocontrol a gain in the delay-lock code tracking loop.
 31. The methodaccording to claim 30, wherein the values of the loop error signal areconstant values capable of being adjusted to control the gain in thedelay-lock code tracking loop.
 32. The method according to claim 23,further comprising the step of utilizing the adaptable threshold levelsto affect a bandwidth of the delay-lock code tracking loop.
 33. Themethod according to claim 23, wherein the delay-lock code tracking loopincludes a receiver sample buffer from which the samples of the receivedcode sequence may be retrieved with different delays, and the methodfurther comprises the step of adjusting a position of the samples in thereceiver sample buffer based on the loop error signal.
 34. The methodaccording to claim 33, further comprising the step of filtering the looperror signal prior to said adjusting step.
 35. An apparatus forgenerating an error signal for a delay-lock code tracking loop in a CDMAsystem, comprising: an accumulator for accumulating sign informationrelating to phase differences between samples of a received codesequence; a comparator for comparing the accumulated sign informationagainst adaptable threshold levels; and an error signal generator forgenerating the error signal when at least one of the adaptable thresholdlevels is satisfied.
 36. The apparatus according to claim 35, furthercomprising an arithmetic module for calculating a first integralcorresponding to products of some of the samples and a scrambling codesequence, calculating a second integral corresponding to products oflater occurring ones of the samples and the scrambling code, andsubtracting the second integral from the first integral.
 37. Theapparatus according to claim 36, wherein each of the first integral andthe second integral are calculated over a code tracking dwell time. 38.The apparatus according to claim 35, wherein said accumulator is foraccumulating the sign information from a sample error signal e[m],wherein e[m] is equal to${\sum\limits_{n = 0}^{N_{D} - 1}{{R_{E}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}{{Sc}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}}} - {\sum\limits_{n = 0}^{N_{D} - 1}{{R_{L}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}{{Sc}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}}}$wherein R_(E) and R_(L) respectively represent earlier occurring samplesand later occurring samples with respect to on-time occurring samples, nis an index of the samples in a chip rate, N_(D) is a code trackingdwell time, Sc is a local scrambling code sequence, and m is an indexfor the sample error signal e[m].
 39. The apparatus according to claim35, wherein said error signal generator is for generating a positiveconstant error signal when a positive threshold is satisfied, andgenerates a negative constant error signal when a negative thresholdlevel is satisfied.
 40. The apparatus according to claim 39, wherein thepositive constant error signal and the negative constant error signalare for controlling a gain of the delay-lock code tracking loop.
 41. Theapparatus according to claim 35, further comprising a receiver samplebuffer for allowing the samples of the received code sequence to beretrieved there from with different delays, and for adjusting positionsof the samples in the buffer based on the error signal.
 42. Theapparatus according to claim 41, further comprising a filter forfiltering the error signal prior to adjusting the positions of thesamples in the receiver sample buffer.
 43. A method for generating aloop error signal for a delay-lock code tracking loop in a CDMA system,comprising the steps of: accumulating sign information relating to phasedifferences between samples of a received code sequence; decimating theaccumulated sign information; and utilizing an output of said decimatingstep as the loop error signal for the delay-lock code tracking loop. 44.The method according to claim 43, wherein the output of said decimatingstep is utilized as the loop error signal upon a decimation of athreshold number of the samples.
 45. The method according to claim 44,further comprising the step of resetting the output of said decimatingstep at a same interval as when the output of said decimating step isutilized as the loop error signal.
 46. The method according to claim 43,further comprising the steps of: calculating a first integralcorresponding to products of some of the samples and a scrambling codesequence; calculating a second integral corresponding to products oflater occurring ones of the samples and the scrambling code; andsubtracting the second integral from the first integral to obtain thesign information.
 47. The method according to claim 46, wherein each ofthe first integral and the second integral are calculated over a codetracking dwell time.
 48. The method according to claim 43, wherein saidaccumulating step accumulates the sign information from a sample errorsignal e[m], wherein e[m] is equal to${\sum\limits_{n = 0}^{N_{D} - 1}{{R_{E}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}{{Sc}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}}} - {\sum\limits_{n = 0}^{N_{D} - 1}{{R_{L}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}{{Sc}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}}}$wherein R_(E) and R_(L) respectively represent earlier occurring samplesand later occurring samples with respect to on-time occurring samples, nis an index of the samples in a chip rate, N_(D) is a code trackingdwell time, Sc is a local scrambling code sequence, and m is an indexfor the sample error signal e[m].
 49. The method according to claim 43,wherein the delay-lock code tracking loop includes a receiver samplebuffer from which the samples of the received code sequence may beretrieved with different delays, and the method further comprises thestep of adjusting a position of the samples in the receiver samplebuffer based on the loop error signal.
 50. The method according to claim43, further comprising the step of filtering the loop error signal priorto said adjusting step.
 51. An apparatus for generating a loop errorsignal for a delay-lock code tracking loop in a CDMA system, comprising:an accumulator for accumulating sign information relating to phasedifferences between samples of a received code sequence; and a decimatorfor receiving the accumulated sign information from said accumulator andfor decimating the accumulated sign information, wherein an output ofsaid decimator is utilized as the loop error signal for the delay-lockcode tracking loop.
 52. The apparatus according to claim 51, wherein theoutput of said decimator is utilized as the loop error signal upon adecimation of a threshold number of the samples.
 53. The apparatusaccording to claim 52, wherein the output of said decimator is reset ata same interval as when the output of said decimator is utilized as theloop error signal.
 54. The apparatus according to claim 51, furthercomprising an arithmetic module for calculating a first integralcorresponding to products of some of the samples and a scrambling codesequence, calculating a second integral corresponding to products oflater occurring ones of the samples and the scrambling code, andsubtracting the second integral from the first integral.
 55. Theapparatus according to claim 54, wherein each of the first integral andthe second integral are calculated over a code tracking dwell time. 56.The apparatus according to claim 51, wherein said accumulator is foraccumulating the sign information from a sample error signal e[m],wherein e[m] is equal to${\sum\limits_{n = 0}^{N_{D} - 1}{{R_{E}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}{{Sc}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}}} - {\sum\limits_{n = 0}^{N_{D} - 1}{{R_{L}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}{{Sc}\left\lbrack {{m\quad N_{D}} + n} \right\rbrack}}}$wherein R_(E) and R_(L) respectively represent earlier occurring samplesand later occurring samples with respect to on-time occurring samples, nis an index of the samples in a chip rate, N_(D) is a code trackingdwell time, Sc is a local scrambling code sequence, and m is an indexfor the sample error signal e[m].
 57. The apparatus according to claim51, further comprising a receiver sample buffer for allowing the samplesof the received code sequence to be retrieved there from with differentdelays, and for adjusting positions of the samples in the buffer basedon the error signal.
 58. The apparatus according to claim 57, furthercomprising a filter for filtering the error signal prior to adjustingthe positions of the samples in the receiver sample buffer.